1. Field of the Invention
The present invention generally relates to physical memory systems and more specifically to systems and methods for addressing physical memory.
2. Description of the Related Art
Modern processing units, such as graphics processing units (GPUs) and central processing units (CPUs), conventionally implement a virtual memory model, which presents a virtual address space to certain client modules within a given processing unit. The virtual address space is organized as a plurality of virtual pages that are each an integral power of two in size. A memory management unit maps virtual pages into physical pages of corresponding size within an attached memory subsystem. The memory subsystem comprises a plurality of discrete memory storage devices, such as dynamic random access memory (DRAM) devices, organized as independently operable partitions. Each partition includes one or more of the DRAM devices. Each physical page is conventionally interleaved over the partitions and further interleaved over DRAM pages associated with the partitions. A conventional memory management unit maps virtual pages into a physical address space comprising an integral power of two partitions. Upper address bits for the virtual page are translated to an arbitrary, page-aligned physical address. Lower address bits for the virtual page that define an address within the virtual page are mapped directly to corresponding physical address bits. This address mapping technique requires a power of two number of identical partitions.
In certain manufacturing scenarios, a technique known in the art as “floor sweeping” is used to yield functionally acceptable processing units that would otherwise be discarded because they include one or more manufacturing faults. Specifically, when the manufacturing faults do not interfere with essential functions, a processing unit may be salvaged and used as a fully functional device with an appropriately reduced functional specification. One common manufacturing fault in processing units occurs in partition circuitry. However, a failed partition typically means that only a non-power of two number of partitions is available, a scenario that is incompatible with requirements of the memory management unit. Without a properly functioning memory management unit, the processor cannot be salvaged via floor sweeping.
Accordingly, what is needed in the art is a technique for enabling virtual addressing in memory subsystems comprising a non-power of two number of operable partitions.